/*************************************************************************
 * Name         : sgxvec34usedefs.h
 * Title        : SGX hw definitions
 *
 * Copyright    : 2005-2006 by Imagination Technologies Limited. All rights reserved.
 *              : No part of this software, either material or conceptual
 *              : may be copied or distributed, transmitted, transcribed,
 *              : stored in a retrieval system or translated into any
 *              : human or computer language in any form by any means,
 *              : electronic, mechanical, manual or other-wise, or
 *              : disclosed to third parties without the express written
 *              : permission of Imagination Technologies Limited, Unit 8, HomePark
 *              : Industrial Estate, King's Langley, Hertfordshire,
 *              : WD4 8LZ, U.K.
 *
 * Platform     : ANSI
 *
 * Modifications:-
 * $Log: sgxvec34usedefs.h $
 **************************************************************************/

#ifndef _SGXVEC34USEDEFS_H_
#define	_SGXVEC34USEDEFS_H_

/*
	Width of each of the hardware's internal registers in dwords.
*/
#define SGXVEC_INTERNAL_REGISTER_WIDTH_IN_DWORDS	(4)

/*
	Register banks.
*/
#define SGXVEC_USE1_D1STDBANK_INDEXED_IL		(3U)		/* Replaces EURASIA_USE1_D1STDBANK_INDEXED */
#define SGXVEC_USE1_D1EXTBANK_INDEXED_IH		(3U)		/* Replaces EURASIA_USE1_D1EXTBANK_FPINTERNAL */

#define SGXVEC_USE0_S1EXTBANK_INDEXED_IL		(0U)		/* Replaces EURASIA_USE0_S1EXTBANK_INDEXED */
#define SGXVEC_USE0_S1EXTBANK_INDEXED_IH		(3U)		/* Replaces EURASIA_USE0_S1EXTBANK_FPINTERNAL */

#define SGXVEC_USE0_S2EXTBANK_INDEXED_IL		(0U)		/* Replaces EURASIA_USE0_S2EXTBANK_INDEXED */
#define SGXVEC_USE0_S2EXTBANK_INDEXED_IH		(3U)		/* Replaces EURASIA_USE0_S2EXTBANK_FPINTERNAL */

/*
	Index register number encoding.
*/
#define SGXVEC_USE_INDEX_OFFSET_SHIFT			(0)
#define SGXVEC_USE_INDEX_OFFSET_CLRMSK			(0xE0U)

#define SGXVEC_USE_INDEX_MAXIMUM_OFFSET			31

#define SGXVEC_USE_FCINDEX_OFFSET_SHIFT			(0)
#define SGXVEC_USE_FCINDEX_OFFSET_CLRMSK		(0xF0U)

#define SGXVEC_USE_FCINDEX_MAXIMUM_OFFSET		15

#define SGXVEC_USE_INDEX_NONOFFSET_NUM_BITS		2

#define SGXVEC_USE_INDEX_NONOFFSET_BANK_SHIFT	(0)
#define SGXVEC_USE_INDEX_NONOFFSET_BANK_CLRMSK	(0xFFFFFFFCU)

/*
	Vector opcodes
*/
#define SGXVEC_USE1_OP_VECMAD					(0U)		/* Replaces EURASIA_USE1_OP_FARITH */
#define SGXVEC_USE1_OP_VECNONMADF32				(1U)		/* Replaces EURASIA_USE1_OP_FSCALAR */
#define SGXVEC_USE1_OP_VECNONMADF16				(2U)		/* Replaces EURASIA_USE1_OP_FDOTPRODUCT */
#define SGXVEC_USE1_OP_SVEC						(3U)		/* Replaces EURASIA_USE1_OP_FMINMAX */
#define SGXVEC_USE1_OP_DVEC3					(4U)		/* Replaces EURASIA_USE1_OP_FGRADIENT */
#define SGXVEC_USE1_OP_DVEC4					(5U)		/* Replaces EURASIA_USE1_OP_MOVC */
#define SGXVEC_USE1_OP_VECCOMPLEX				(6U)		/* Replaces EURASIA_USE1_OP_FARITH16 */
#define SGXVEC_USE1_OP_VECMOV					(7U)		/* Replaces EURASIA_USE1_OP_EFO */

/*
	Defines for 64-bit unified store registers.
*/
#define SGXVEC_USE_VEC2_REGISTER_NUMBER_MAX			(64)
#define SGXVEC_USE_VEC2_REGISTER_NUMBER_MASK		(0x3F)
#define SGXVEC_USE_VEC2_REGISTER_NUMBER_ALIGNSHIFT	(1)
#define SGXVEC_USE_VEC2_REGISTER_NUMBER_ALIGN		(1 << SGXVEC_USE_VEC2_REGISTER_NUMBER_ALIGNSHIFT)

/* The number field is effectively 7 bits long but the LSB is always zero. */
#define SGXVEC_USE_VEC2_REGISTER_NUMBER_BITS			(6)
#define SGXVEC_USE_VEC2_REGISTER_NUMBER_FIELD_LENGTH	(SGXVEC_USE_VEC2_REGISTER_NUMBER_BITS + 1)

/* 
	The maximum unified store register number (in 32-bit units) which can be used in the
	wide (able to access a 128-bit vector) unified store source to VDP3, VDP4, VMAD3, VMAD4, the
	dual-issue vector instruction and the two source vector instructions.
*/
#define SGXVEC_USE_VEC2_WIDE_USSOURCE_REGISTER_NUMBER_MAX	(124)

/*
	Channel write mask definitions for F16/F32 vector instructions.
*/
#define SGXVEC_USE1_VEC_DMSK_GPI_WRITEX			(0x1)
#define SGXVEC_USE1_VEC_DMSK_GPI_WRITEY			(0x2)
#define SGXVEC_USE1_VEC_DMSK_GPI_WRITEZ			(0x4)
#define SGXVEC_USE1_VEC_DMSK_GPI_WRITEW			(0x8)

#define SGXVEC_USE1_VEC_DMSK_F32US_WRITEX		(0x1)
#define SGXVEC_USE1_VEC_DMSK_F32US_WRITEY		(0x2)

#define SGXVEC_USE1_VEC_DMSK_F16US_WRITEXY		(0x1)
#define SGXVEC_USE1_VEC_DMSK_F16US_WRITEZW		(0x4)

#define SGXVEC_USE1_VEC_DMSK_C10US_WRITEXYZW	(0xF)

/*
	Vector MAD instruction
*/
#define SGXVEC_USE1_VECMAD_F16						(0x04000000U)

#define SGXVEC_USE1_VECMAD_SVPRED_SHIFT				(24)
#define SGXVEC_USE1_VECMAD_SVPRED_CLRMSK			(0xFCFFFFFFU)

#define SGXVEC_USE1_VECMAD_SRC0SWIZ_BIT2_SHIFT		(21)
#define SGXVEC_USE1_VECMAD_SRC0SWIZ_BIT2_CLRMSK		(0xFFDFFFFFU)

#define SGXVEC_USE1_VECMAD_SRC0ABS					(0x00040000U)

#define SGXVEC_USE1_VECMAD_SRC2SWIZ_BITS02_SHIFT	(13)
#define SGXVEC_USE1_VECMAD_SRC2SWIZ_BITS02_CLRMSK	(0xFFFF1FFFU)

#define SGXVEC_USE1_VECMAD_SRC1SWIZ_BIT2_SHIFT		(12)
#define SGXVEC_USE1_VECMAD_SRC1SWIZ_BIT2_CLRMSK		(0xFFFFEFFFU)

#define SGXVEC_USE1_VECMAD_NOSCHED					(0x00000800U)

#define SGXVEC_USE1_VECMAD_DMSK_SHIFT				(7)
#define SGXVEC_USE1_VECMAD_DMSK_CLRMSK				(0xFFFFF87FU)

#define SGXVEC_USE1_VECMAD_SRC1MOD_SHIFT			(5)
#define SGXVEC_USE1_VECMAD_SRC1MOD_CLRMSK			(0xFFFFFF9FU)

#define SGXVEC_USE1_VECMAD_SRC2MOD_SHIFT			(3)
#define SGXVEC_USE1_VECMAD_SRC2MOD_CLRMSK			(0xFFFFFFE7U)

#define SGXVEC_USE0_VECMAD_DST_SHIFT				(22)
#define SGXVEC_USE0_VECMAD_DST_CLRMSK				(0xF03FFFFFU)

#define SGXVEC_USE0_VECMAD_SRC1SWIZ_BITS01_SHIFT	(20)
#define SGXVEC_USE0_VECMAD_SRC1SWIZ_BITS01_CLRMSK	(0xFFCFFFFFU)

#define SGXVEC_USE0_VECMAD_SRC0SWIZ_BITS01_SHIFT	(18)
#define SGXVEC_USE0_VECMAD_SRC0SWIZ_BITS01_CLRMSK	(0xFFF3FFFFU)

#define SGXVEC_USE0_VECMAD_SRC0_SHIFT				(12)
#define SGXVEC_USE0_VECMAD_SRC0_CLRMSK				(0xFFFC0FFFU)

#define SGXVEC_USE0_VECMAD_SRC1_SHIFT				(6)
#define SGXVEC_USE0_VECMAD_SRC1_CLRMSK				(0xFFFFF03FU)

#define SGXVEC_USE0_VECMAD_SRC2_SHIFT				(0)
#define SGXVEC_USE0_VECMAD_SRC2_CLRMSK				(0xFFFFFFC0U)

/*
	Vector MAD swizzle.
*/
#define SGXVEC_USE_VECMAD_SRC0SWIZZLE_XXXX			(0)
#define SGXVEC_USE_VECMAD_SRC0SWIZZLE_YYYY			(1)
#define SGXVEC_USE_VECMAD_SRC0SWIZZLE_ZZZZ			(2)
#define SGXVEC_USE_VECMAD_SRC0SWIZZLE_WWWW			(3)
#define SGXVEC_USE_VECMAD_SRC0SWIZZLE_XYZW			(4)
#define SGXVEC_USE_VECMAD_SRC0SWIZZLE_YZXW			(5)
#define SGXVEC_USE_VECMAD_SRC0SWIZZLE_XYWW			(6)
#define SGXVEC_USE_VECMAD_SRC0SWIZZLE_ZWXY			(7)

#define SGXVEC_USE_VECMAD_SRC1SWIZZLE_XXXX			(0)
#define SGXVEC_USE_VECMAD_SRC1SWIZZLE_YYYY			(1)
#define SGXVEC_USE_VECMAD_SRC1SWIZZLE_ZZZZ			(2)
#define SGXVEC_USE_VECMAD_SRC1SWIZZLE_WWWW			(3)
#define SGXVEC_USE_VECMAD_SRC1SWIZZLE_XYZW			(4)
#define SGXVEC_USE_VECMAD_SRC1SWIZZLE_XYYZ			(5)
#define SGXVEC_USE_VECMAD_SRC1SWIZZLE_YYWW			(6)
#define SGXVEC_USE_VECMAD_SRC1SWIZZLE_WYZW			(7)

#define SGXVEC_USE_VECMAD_SRC2SWIZZLE_XXXX			(0)
#define SGXVEC_USE_VECMAD_SRC2SWIZZLE_YYYY			(1)
#define SGXVEC_USE_VECMAD_SRC2SWIZZLE_ZZZZ			(2)
#define SGXVEC_USE_VECMAD_SRC2SWIZZLE_WWWW			(3)
#define SGXVEC_USE_VECMAD_SRC2SWIZZLE_XYZW			(4)
#define SGXVEC_USE_VECMAD_SRC2SWIZZLE_XZWW			(5)
#define SGXVEC_USE_VECMAD_SRC2SWIZZLE_XXYZ			(6)
#define SGXVEC_USE_VECMAD_SRC2SWIZZLE_XYZZ			(7)

/*
	F16/F32 vec4 instructions
*/
#define SGXVEC_USE1_VECNONMAD_EVPRED_SHIFT				(24)
#define SGXVEC_USE1_VECNONMAD_EVPRED_CLRMSK				(0xF8FFFFFFU)

#define SGXVEC_USE1_VECNONMAD_SRC1SWIZ_BITS1011_SHIFT	(21)
#define SGXVEC_USE1_VECNONMAD_SRC1SWIZ_BITS1011_CLRMSK	(0xFF9FFFFFU)

#define SGXVEC_USE1_VECNONMAD_SRC1SWIZ_BIT9_SHIFT		(18)
#define SGXVEC_USE1_VECNONMAD_SRC1SWIZ_BIT9_CLRMSK		(0xFFFBFFFFU)

#define SGXVEC_USE1_VECNONMAD_SRC2SWIZ_SHIFT			(12)
#define SGXVEC_USE1_VECNONMAD_SRC2SWIZ_CLRMSK			(0xFFFF0FFFU)

#define SGXVEC_USE1_VECNONMAD_NOSCHED					(0x00000800U)

#define SGXVEC_USE1_VECNONMAD_DMASK_SHIFT				(7)
#define SGXVEC_USE1_VECNONMAD_DMASK_CLRMSK				(0xFFFFF87FU)

#define SGXVEC_USE1_VECNONMAD_SRC1MOD_SHIFT				(5)
#define SGXVEC_USE1_VECNONMAD_SRC1MOD_CLRMSK			(0xFFFFFF9FU)

#define SGXVEC_USE1_VECNONMAD_SRC2ABS					(0x00000010U)

#define SGXVEC_USE1_VECNONMAD_SRC1SWIZ_BIT78_SHIFT		(2)
#define SGXVEC_USE1_VECNONMAD_SRC1SWIZ_BIT78_CLRMSK		(0xFFFFFFF3U)

#define SGXVEC_USE0_VECNONMAD_DST_SHIFT					(22)
#define SGXVEC_USE0_VECNONMAD_DST_CLRMSK				(0xF03FFFFFU)

#define SGXVEC_USE0_VECNONMAD_SRC1SWIZ_BITS06_SHIFT		(15)
#define SGXVEC_USE0_VECNONMAD_SRC1SWIZ_BITS06_CLRMSK	(0xFFC07FFFU)

#define SGXVEC_USE0_VECNONMAD_OP2_SHIFT					(12)
#define SGXVEC_USE0_VECNONMAD_OP2_CLRMSK				(0xFFFF8FFFU)

#define SGXVEC_USE0_VECNONMAD_OP2_VMUL					(0)
#define SGXVEC_USE0_VECNONMAD_OP2_VADD					(1)
#define SGXVEC_USE0_VECNONMAD_OP2_VFRC					(2)
#define SGXVEC_USE0_VECNONMAD_OP2_VDSX					(3)
#define SGXVEC_USE0_VECNONMAD_OP2_VDSY					(4)
#define SGXVEC_USE0_VECNONMAD_OP2_VMIN					(5)
#define SGXVEC_USE0_VECNONMAD_OP2_VMAX					(6)
#define SGXVEC_USE0_VECNONMAD_OP2_VDP					(7)

#define SGXVEC_USE0_VECNONMAD_SRC1_SHIFT				(6)
#define SGXVEC_USE0_VECNONMAD_SRC1_CLRMSK				(0xFFFFF03FU)

#define SGXVEC_USE0_VECNONMAD_SRC2_SHIFT				(0)
#define SGXVEC_USE0_VECNONMAD_SRC2_CLRMSK				(0xFFFFFFC0U)

/*
	Defines for the channels within a source 1 swizzle.
*/
#define SGXVEC_USE_VECNONMAD_SRC1SWIZ_X_SHIFT			(0)
#define SGXVEC_USE_VECNONMAD_SRC1SWIZ_X_CLRMSK			(0xFF8U)

#define SGXVEC_USE_VECNONMAD_SRC1SWIZ_Y_SHIFT			(3)
#define SGXVEC_USE_VECNONMAD_SRC1SWIZ_Y_CLRMSK			(0xFC7U)

#define SGXVEC_USE_VECNONMAD_SRC1SWIZ_Z_SHIFT			(6)
#define SGXVEC_USE_VECNONMAD_SRC1SWIZ_Z_CLRMSK			(0xE3FU)

#define SGXVEC_USE_VECNONMAD_SRC1SWIZ_W_SHIFT			(9)
#define SGXVEC_USE_VECNONMAD_SRC1SWIZ_W_CLRMSK			(0x1FFU)

/*
	Defines for the possible selections for each channel of a
	source 1 swizzle.
*/
#define SGXVEC_USE_VECNONMAD_SRC1SWIZ_SEL_X				(0)
#define SGXVEC_USE_VECNONMAD_SRC1SWIZ_SEL_Y				(1)
#define SGXVEC_USE_VECNONMAD_SRC1SWIZ_SEL_Z				(2)
#define SGXVEC_USE_VECNONMAD_SRC1SWIZ_SEL_W				(3)
#define SGXVEC_USE_VECNONMAD_SRC1SWIZ_SEL_0				(4)
#define SGXVEC_USE_VECNONMAD_SRC1SWIZ_SEL_1				(5)
#define SGXVEC_USE_VECNONMAD_SRC1SWIZ_SEL_2				(6)
#define SGXVEC_USE_VECNONMAD_SRC1SWIZ_SEL_HALF			(7)

/*
	Possible source 2 swizzles.
*/
#define SGXVEC_USE_VECNONMAD_SRC2_SWIZ_XXXX				(0)
#define SGXVEC_USE_VECNONMAD_SRC2_SWIZ_YYYY				(1)
#define SGXVEC_USE_VECNONMAD_SRC2_SWIZ_ZZZZ				(2)
#define SGXVEC_USE_VECNONMAD_SRC2_SWIZ_WWWW				(3)
#define SGXVEC_USE_VECNONMAD_SRC2_SWIZ_XYZW				(4)
#define SGXVEC_USE_VECNONMAD_SRC2_SWIZ_YZWW				(5)
#define SGXVEC_USE_VECNONMAD_SRC2_SWIZ_XYZZ				(6)
#define SGXVEC_USE_VECNONMAD_SRC2_SWIZ_XXYZ				(7)
#define SGXVEC_USE_VECNONMAD_SRC2_SWIZ_XYXY				(8)
#define SGXVEC_USE_VECNONMAD_SRC2_SWIZ_XYWZ				(9)
#define SGXVEC_USE_VECNONMAD_SRC2_SWIZ_ZXYW				(10)
#define SGXVEC_USE_VECNONMAD_SRC2_SWIZ_ZWZW				(11)
#define SGXVEC_USE_VECNONMAD_SRC2_SWIZ_YZXZ				(12)
#define SGXVEC_USE_VECNONMAD_SRC2_SWIZ_XXYY				(13)
#define SGXVEC_USE_VECNONMAD_SRC2_SWIZ_XZWW				(14)
#define SGXVEC_USE_VECNONMAD_SRC2_SWIZ_XYZ1				(15)

/*
	Single issue vec3/vec4 instruction
*/
#define SGXVEC_USE1_SVEC_EVPRED_SHIFT			(24)
#define SGXVEC_USE1_SVEC_EVPRED_CLRMSK			(0xF8FFFFFFU)

#define SGXVEC_USE1_SVEC_VDP34_CENABLE			(0x00400000U)

#define SGXVEC_USE1_SVEC_VMAD34_GPI1SWIZEXT		(0x00400000U)

#define SGXVEC_USE1_SVEC_OP2_SHIFT				(20)
#define SGXVEC_USE1_SVEC_OP2_CLRMSK				(0xFFCFFFFFU)

#define SGXVEC_USE1_SVEC_OP2_DP3				(0)
#define SGXVEC_USE1_SVEC_OP2_DP4				(1)
#define SGXVEC_USE1_SVEC_OP2_VMAD3				(2)
#define SGXVEC_USE1_SVEC_OP2_VMAD4				(3)

#define SGXVEC_USE1_SVEC_USSBEXT				(0x00020000U)

#define SGXVEC_USE1_SVEC_INCCTL_SHIFT			(15)
#define SGXVEC_USE1_SVEC_INCCTL_CLRMSK			(0xFFFE7FFFU)
#define SGXVEC_USE1_SVEC_INCCTL_USONLY			(0)
#define SGXVEC_USE1_SVEC_INCCTL_GPIONLY			(1)
#define SGXVEC_USE1_SVEC_INCCTL_BOTH			(2)
#define SGXVEC_USE1_SVEC_INCCTL_MOE				(3)

#define SGXVEC_USE1_SVEC_GPI0ABS				(0x00004000U)

#define SGXVEC_USE1_SVEC_RCNT_SHIFT				(12)
#define SGXVEC_USE1_SVEC_RCNT_CLRMSK			(0xFFFFCFFFU)
#define SGXVEC_USE1_SVEC_RCNT_MAXIMUM			(4)

#define SGXVEC_USE1_SVEC_NOSCHED				(0x00000800U)

#define SGXVEC_USE1_SVEC_WMSK_SHIFT				(7)
#define SGXVEC_USE1_SVEC_WMSK_CLRMSK			(0xFFFFF87FU)

#define SGXVEC_USE1_SVEC_USSNEG					(0x00000040U)

#define SGXVEC_USE1_SVEC_USSABS					(0x00000020U)

#define SGXVEC_USE1_SVEC_VDP34_CPLANE_SHIFT		(2)
#define SGXVEC_USE1_SVEC_VDP34_CPLANE_CLRMSK	(0xFFFFFFE3U)
#define SGXVEC_USE1_SVEC_VDP34_CPLANE_MAXIMUM	(7)

#define SGXVEC_USE1_SVEC_VMAD34_GPI1NEG			(0x00000010U)

#define SGXVEC_USE1_SVEC_VMAD34_GPI1ABS			(0x00000008U)

#define SGXVEC_USE1_SVEC_VMAD34_GPI0SWIZEXT		(0x00000004U)

#define SGXVEC_USE0_SVEC_GPI0NUM_SHIFT			(28)
#define SGXVEC_USE0_SVEC_GPI0NUM_CLRMSK			(0xCFFFFFFFU)

#define SGXVEC_USE0_SVEC_DST_SHIFT				(22)
#define SGXVEC_USE0_SVEC_DST_CLRMSK				(0xF03FFFFFU)

#define SGXVEC_USE0_SVEC_GPI0SWIZ_SHIFT			(18)
#define SGXVEC_USE0_SVEC_GPI0SWIZ_CLRMSK		(0xFFC3FFFFU)

#define SGXVEC_USE0_SVEC_VDP34_USSWIZW_SHIFT	(15)
#define SGXVEC_USE0_SVEC_VDP34_USSWIZW_CLRMSK	(0xFFFC7FFFU)

#define SGXVEC_USE0_SVEC_VDP34_USSWIZZ_SHIFT	(12)
#define SGXVEC_USE0_SVEC_VDP34_USSWIZZ_CLRMSK	(0xFFFF8FFFU)

#define SGXVEC_USE0_SVEC_VDP34_USSWIZY_SHIFT	(9)
#define SGXVEC_USE0_SVEC_VDP34_USSWIZY_CLRMSK	(0xFFFFF1FFU)

#define SGXVEC_USE0_SVEC_VDP34_USSWIZX_SHIFT	(6)
#define SGXVEC_USE0_SVEC_VDP34_USSWIZX_CLRMSK	(0xFFFFFE3FU)

#define SGXVEC_USE0_SVEC_VMAD34_GPI1SWIZ_SHIFT	(14)
#define SGXVEC_USE0_SVEC_VMAD34_GPI1SWIZ_CLRMSK	(0xFFFC3FFFU)

#define SGXVEC_USE0_SVEC_VMAD34_GPI1NUM_SHIFT	(12)
#define SGXVEC_USE0_SVEC_VMAD34_GPI1NUM_CLRMSK	(0xFFFFCFFFU)

#define SGXVEC_USE0_SVEC_VMAD34_USSWIZEXT		(0x00000400U)

#define SGXVEC_USE0_SVEC_VMAD34_USSWIZ_SHIFT	(6)
#define SGXVEC_USE0_SVEC_VMAD34_USSWIZ_CLRMSK	(0xFFFFFC3FU)

#define SGXVEC_USE0_SVEC_USNUM_SHIFT			(0)
#define SGXVEC_USE0_SVEC_USNUM_CLRMSK			(0xFFFFFFC0U)

#define SGXVEC_USE_SVEC_USSRC_SWIZSEL_X			(0)
#define SGXVEC_USE_SVEC_USSRC_SWIZSEL_Y			(1)
#define SGXVEC_USE_SVEC_USSRC_SWIZSEL_Z			(2)
#define SGXVEC_USE_SVEC_USSRC_SWIZSEL_W			(3)
#define SGXVEC_USE_SVEC_USSRC_SWIZSEL_0			(4)
#define SGXVEC_USE_SVEC_USSRC_SWIZSEL_1			(5)
#define SGXVEC_USE_SVEC_USSRC_SWIZSEL_2			(6)
#define SGXVEC_USE_SVEC_USSRC_SWIZSEL_HALF		(7)

/*
	Dual issue vector instruction
*/

#define SGXVEC_USE1_DVEC_GPI1NEG				(0x04000000U)

#define SGXVEC_USE1_DVEC_SVPRED_SHIFT			(24)
#define SGXVEC_USE1_DVEC_SVPRED_CLRMSK			(0xFCFFFFFFU)

#define SGXVEC_USE1_DVEC3_OP1EXT				(0x00400000U)

#define SGXVEC_USE1_DVEC4_WMSKW					(0x00400000U)

#define SGXVEC_USE1_DVEC_F16					(0x00200000U)

#define SGXVEC_USE1_DVEC_GPI1SWIZEXT			(0x00100000U)

#define SGXVEC_USE1_DVEC_USSWIZ_SHIFT			(16)
#define SGXVEC_USE1_DVEC_USSWIZ_CLRMSK			(0xFFF0FFFFU)

#define SGXVEC_USE1_DVEC_USNEG					(0x00008000U)

#define SGXVEC_USE1_DVEC_OP1_SHIFT				(12)
#define SGXVEC_USE1_DVEC_OP1_CLRMSK				(0xFFFF8FFFU)

#define SGXVEC_USE1_DVEC_OP1_STD_VMAD			(0)
#define SGXVEC_USE1_DVEC_OP1_STD_VDP			(1)
#define SGXVEC_USE1_DVEC_OP1_STD_VSSQ			(2)
#define SGXVEC_USE1_DVEC_OP1_STD_VMUL			(3)
#define SGXVEC_USE1_DVEC_OP1_STD_VADD			(4)
#define SGXVEC_USE1_DVEC_OP1_STD_VMOV			(5)
#define SGXVEC_USE1_DVEC_OP1_STD_FRSQ			(6)
#define SGXVEC_USE1_DVEC_OP1_STD_FRCP			(7)

#define SGXVEC_USE1_DVEC_OP1_EXT_FMAD			(0)
#define SGXVEC_USE1_DVEC_OP1_EXT_FADD			(1)
#define SGXVEC_USE1_DVEC_OP1_EXT_FMUL			(2)
#define SGXVEC_USE1_DVEC_OP1_EXT_FSUBFLR		(3)
#define SGXVEC_USE1_DVEC_OP1_EXT_FEXP			(4)
#define SGXVEC_USE1_DVEC_OP1_EXT_FLOG			(5)
#define SGXVEC_USE1_DVEC_OP1_EXT_RESERVED0		(6)
#define SGXVEC_USE1_DVEC_OP1_EXT_RESERVED1		(7)

#define SGXVEC_USE1_DVEC_OP2EXT					(0x00000800U)

#define SGXVEC_USE1_DVEC_DCFG_PRIWRITETOUS		(0x00000400U)

#define SGXVEC_USE1_DVEC_GPI0SWIZ_SHIFT			(6)
#define SGXVEC_USE1_DVEC_GPI0SWIZ_CLRMSK		(0xFFFFFC3FU)

#define SGXVEC_USE1_DVEC_GPI1SWIZ_SHIFT			(2)
#define SGXVEC_USE1_DVEC_GPI1SWIZ_CLRMSK		(0xFFFFFFC3U)

#define SGXVEC_USE0_DVEC_GPIDNUM_SHIFT			(28)
#define SGXVEC_USE0_DVEC_GPIDNUM_CLRMSK			(0xCFFFFFFFU)

#define SGXVEC_USE0_DVEC_OP2_SHIFT				(18)
#define SGXVEC_USE0_DVEC_OP2_CLRMSK				(0xFFE3FFFFU)

#define SGXVEC_USE0_DVEC_OP2_STD_RESERVED		(0)
#define SGXVEC_USE0_DVEC_OP2_STD_VDP			(1)
#define SGXVEC_USE0_DVEC_OP2_STD_VSSQ			(2)
#define SGXVEC_USE0_DVEC_OP2_STD_VMUL			(3)
#define SGXVEC_USE0_DVEC_OP2_STD_VADD			(4)
#define SGXVEC_USE0_DVEC_OP2_STD_VMOV			(5)
#define SGXVEC_USE0_DVEC_OP2_STD_FRSQ			(6)
#define SGXVEC_USE0_DVEC_OP2_STD_FRCP			(7)

#define SGXVEC_USE0_DVEC_OP2_EXT_FMAD			(0)
#define SGXVEC_USE0_DVEC_OP2_EXT_FADD			(1)
#define SGXVEC_USE0_DVEC_OP2_EXT_FMUL			(2)
#define SGXVEC_USE0_DVEC_OP2_EXT_FSUBFLR		(3)
#define SGXVEC_USE0_DVEC_OP2_EXT_FEXP			(4)
#define SGXVEC_USE0_DVEC_OP2_EXT_FLOG			(5)
#define SGXVEC_USE0_DVEC_OP2_EXT_RESERVED0		(6)
#define SGXVEC_USE0_DVEC_OP2_EXT_RESERVED1		(7)

#define SGXVEC_USE0_DVEC_SRCCFG_SHIFT			(16)
#define SGXVEC_USE0_DVEC_SRCCFG_CLRMSK			(0xFFFCFFFFU)
#define SGXVEC_USE0_DVEC_SRCCFG_SRC0			(0)
#define SGXVEC_USE0_DVEC_SRCCFG_SRC1			(1)
#define SGXVEC_USE0_DVEC_SRCCFG_SRC2			(2)
#define SGXVEC_USE0_DVEC_SRCCFG_NONE			(3)

/* Count of source configuration options available. */
#define SGXVEC_USE0_DVEC_SRCCFG_COUNT			(4)

/* Maximum number of sources to a dual-issued OP1. */
#define SGXVEC_USE_DVEC_OP1_MAXIMUM_SRC_COUNT	(3)

/* Maximum number of sources to a dual-issued OP2. */
#define SGXVEC_USE_DVEC_OP2_MAXIMUM_SRC_COUNT	(3)

#define SGXVEC_USE0_DVEC_GPI2NUM_SHIFT			(14)
#define SGXVEC_USE0_DVEC_GPI2NUM_CLRMSK			(0xFFFF3FFFU)
#define SGXVEC_USE0_DVEC_GPI2NUM_DEFAULT		(2)

#define SGXVEC_USE0_DVEC_USSWIZEXT				(0x00008000U)

#define SGXVEC_USE0_DVEC_USABS					(0x00004000U)

#define SGXVEC_USE0_DVEC_GPI1NUM_SHIFT			(12)
#define SGXVEC_USE0_DVEC_GPI1NUM_CLRMSK			(0xFFFFCFFFU)

#define SGXVEC_USE0_DVEC_GPI0NUM_SHIFT			(10)
#define SGXVEC_USE0_DVEC_GPI0NUM_CLRMSK			(0xFFFFF3FFU)

#define SGXVEC_USE0_DVEC_WMSK_SHIFT				(7)
#define SGXVEC_USE0_DVEC_WMSK_CLRMSK			(0xFFFFFC7FU)

#define SGXVEC_USE0_DVEC_USSNUM_SHIFT			(0)
#define SGXVEC_USE0_DVEC_USSNUM_CLRMSK			(0xFFFFFF80U)

/*
	Length of the unified store source register number field for a dual-issued vector instruction.
*/
#define SGXVEC_USE_DVEC_USSRC_VECTOR_REGISTER_NUMBER_BITS	(8)

/*
	Length of the unified store source register number field for a dual-issued scalar instruction.
*/
#define SGXVEC_USE_DVEC_USSRC_SCALAR_REGISTER_NUMBER_BITS	(7)

/*
	Length of the unified store destination register number field for a dual-issued vector instruction.
*/
#define SGXVEC_USE_DVEC_USDEST_VECTOR_REGISTER_NUMBER_BITS	(8)

/*
	Dual-issue vector vec3 standard swizzles.
*/
#define SGXVEC_USE_DVEC_SWIZ_VEC3_STD_XXX		(0)
#define SGXVEC_USE_DVEC_SWIZ_VEC3_STD_YYY		(1)
#define SGXVEC_USE_DVEC_SWIZ_VEC3_STD_ZZZ		(2)
#define SGXVEC_USE_DVEC_SWIZ_VEC3_STD_WWW		(3)
#define SGXVEC_USE_DVEC_SWIZ_VEC3_STD_XYZ		(4)
#define SGXVEC_USE_DVEC_SWIZ_VEC3_STD_YZW		(5)
#define SGXVEC_USE_DVEC_SWIZ_VEC3_STD_XXY		(6)
#define SGXVEC_USE_DVEC_SWIZ_VEC3_STD_XYX		(7)
#define SGXVEC_USE_DVEC_SWIZ_VEC3_STD_YYX		(8)
#define SGXVEC_USE_DVEC_SWIZ_VEC3_STD_YYZ		(9)
#define SGXVEC_USE_DVEC_SWIZ_VEC3_STD_ZXY		(10)
#define SGXVEC_USE_DVEC_SWIZ_VEC3_STD_XZY		(11)
#define SGXVEC_USE_DVEC_SWIZ_VEC3_STD_000		(12)
#define SGXVEC_USE_DVEC_SWIZ_VEC3_STD_HALFHALFHALF		(13)
#define SGXVEC_USE_DVEC_SWIZ_VEC3_STD_111		(14)
#define SGXVEC_USE_DVEC_SWIZ_VEC3_STD_222		(15)

/*
	Dual-issue vector vec3 extended swizzles.
*/
#define SGXVEC_USE_DVEC_SWIZ_VEC3_EXT_XYY		(0)
#define SGXVEC_USE_DVEC_SWIZ_VEC3_EXT_YXY		(1)
#define SGXVEC_USE_DVEC_SWIZ_VEC3_EXT_XXZ		(2)
#define SGXVEC_USE_DVEC_SWIZ_VEC3_EXT_YXX		(3)
#define SGXVEC_USE_DVEC_SWIZ_VEC3_EXT_XY0		(4)
#define SGXVEC_USE_DVEC_SWIZ_VEC3_EXT_X10		(5)
#define SGXVEC_USE_DVEC_SWIZ_VEC3_EXT_XZY		(6)
#define SGXVEC_USE_DVEC_SWIZ_VEC3_EXT_YZX		(7)
#define SGXVEC_USE_DVEC_SWIZ_VEC3_EXT_ZYX		(8)
#define SGXVEC_USE_DVEC_SWIZ_VEC3_EXT_ZZY		(9)
#define SGXVEC_USE_DVEC_SWIZ_VEC3_EXT_XY1		(10)
#define SGXVEC_USE_DVEC_SWIZ_VEC3_EXT_RESERVED0	(11)
#define SGXVEC_USE_DVEC_SWIZ_VEC3_EXT_RESERVED1	(12)
#define SGXVEC_USE_DVEC_SWIZ_VEC3_EXT_RESERVED2	(13)
#define SGXVEC_USE_DVEC_SWIZ_VEC3_EXT_RESERVED3	(14)
#define SGXVEC_USE_DVEC_SWIZ_VEC3_EXT_RESERVED4	(15)

/*
	Dual-issue vector vec4 standard swizzles.
*/
#define SGXVEC_USE_DVEC_SWIZ_VEC4_STD_XXXX		(0)
#define SGXVEC_USE_DVEC_SWIZ_VEC4_STD_YYYY		(1)
#define SGXVEC_USE_DVEC_SWIZ_VEC4_STD_ZZZZ		(2)
#define SGXVEC_USE_DVEC_SWIZ_VEC4_STD_WWWW		(3)
#define SGXVEC_USE_DVEC_SWIZ_VEC4_STD_XYZW		(4)
#define SGXVEC_USE_DVEC_SWIZ_VEC4_STD_YZWW		(5)
#define SGXVEC_USE_DVEC_SWIZ_VEC4_STD_XYZZ		(6)
#define SGXVEC_USE_DVEC_SWIZ_VEC4_STD_XXYZ		(7)
#define SGXVEC_USE_DVEC_SWIZ_VEC4_STD_XYXY		(8)
#define SGXVEC_USE_DVEC_SWIZ_VEC4_STD_XYWZ		(9)
#define SGXVEC_USE_DVEC_SWIZ_VEC4_STD_ZXYW		(10)
#define SGXVEC_USE_DVEC_SWIZ_VEC4_STD_ZWZW		(11)
#define SGXVEC_USE_DVEC_SWIZ_VEC4_STD_0000		(12)
#define SGXVEC_USE_DVEC_SWIZ_VEC4_STD_HALFHALFHALFHALF	(13)
#define SGXVEC_USE_DVEC_SWIZ_VEC4_STD_1111		(14)
#define SGXVEC_USE_DVEC_SWIZ_VEC4_STD_2222		(15)

/*
	Dual-issue vector vec4 extended swizzles.
*/
#define SGXVEC_USE_DVEC_SWIZ_VEC4_EXT_YZXW		(0)
#define SGXVEC_USE_DVEC_SWIZ_VEC4_EXT_ZWXY		(1)
#define SGXVEC_USE_DVEC_SWIZ_VEC4_EXT_XZWY		(2)
#define SGXVEC_USE_DVEC_SWIZ_VEC4_EXT_YYWW		(3)
#define SGXVEC_USE_DVEC_SWIZ_VEC4_EXT_WYZW		(4)
#define SGXVEC_USE_DVEC_SWIZ_VEC4_EXT_WZWZ		(5)
#define SGXVEC_USE_DVEC_SWIZ_VEC4_EXT_XYZX		(6)
#define SGXVEC_USE_DVEC_SWIZ_VEC4_EXT_ZZWW		(7)
#define SGXVEC_USE_DVEC_SWIZ_VEC4_EXT_XWZX		(8)
#define SGXVEC_USE_DVEC_SWIZ_VEC4_EXT_YYYX		(9)
#define SGXVEC_USE_DVEC_SWIZ_VEC4_EXT_YYYZ		(10)
#define SGXVEC_USE_DVEC_SWIZ_VEC4_EXT_ZWZW		(11)
#define SGXVEC_USE_DVEC_SWIZ_VEC4_EXT_YZXZ		(12)
#define SGXVEC_USE_DVEC_SWIZ_VEC4_EXT_XXYY		(13)
#define SGXVEC_USE_DVEC_SWIZ_VEC4_EXT_XZWW		(14)
#define SGXVEC_USE_DVEC_SWIZ_VEC4_EXT_XYZ1		(15)

/*
	Vector complex-op instruction.
*/
#define SGXVEC_USE1_VECCOMPLEXOP_DDTYPE_SHIFT		(21)
#define SGXVEC_USE1_VECCOMPLEXOP_DDTYPE_CLRMSK		(0xFF9FFFFFU)
#define SGXVEC_USE1_VECCOMPLEXOP_DDTYPE_F32			(0)
#define SGXVEC_USE1_VECCOMPLEXOP_DDTYPE_F16			(1)
#define SGXVEC_USE1_VECCOMPLEXOP_DDTYPE_C10			(2)
#define SGXVEC_USE1_VECCOMPLEXOP_DDTYPE_RESERVED	(3)

#define SGXVEC_USE1_VECCOMPLEXOP_RCNT_SHIFT			(12)
#define SGXVEC_USE1_VECCOMPLEXOP_RCNT_CLRMSK		(0xFFFF0FFFU)
#define SGXVEC_USE1_VECCOMPLEXOP_RCNT_MAXIMUM		(16)

#define SGXVEC_USE1_VECCOMPLEXOP_NOSCHED			(0x00000800U)

#define SGXVEC_USE1_VECCOMPLEXOP_OP2_SHIFT			(9)
#define SGXVEC_USE1_VECCOMPLEXOP_OP2_CLRMSK			(0xFFFFF9FFU)
#define SGXVEC_USE1_VECCOMPLEXOP_OP2_RCP			(0)
#define SGXVEC_USE1_VECCOMPLEXOP_OP2_RSQ			(1)
#define SGXVEC_USE1_VECCOMPLEXOP_OP2_LOG			(2)
#define SGXVEC_USE1_VECCOMPLEXOP_OP2_EXP			(3)

#define SGXVEC_USE1_VECCOMPLEXOP_SDTYPE_SHIFT		(7)
#define SGXVEC_USE1_VECCOMPLEXOP_SDTYPE_CLRMSK		(0xFFFFFE7FU)
#define SGXVEC_USE1_VECCOMPLEXOP_SDTYPE_F32			(0)
#define SGXVEC_USE1_VECCOMPLEXOP_SDTYPE_F16			(1)
#define SGXVEC_USE1_VECCOMPLEXOP_SDTYPE_C10			(2)
#define SGXVEC_USE1_VECCOMPLEXOP_SDTYPE_RESERVED	(3)

#define SGXVEC_USE1_VECCOMPLEXOP_SRC1MOD_SHIFT		(5)
#define SGXVEC_USE1_VECCOMPLEXOP_SRC1MOD_CLRMSK		(0xFFFFFF9FU)

#define SGXVEC_USE1_VECCOMPLEXOP_SRCCHANSEL_SHIFT	(3)
#define SGXVEC_USE1_VECCOMPLEXOP_SRCCHANSEL_CLRMSK	(0xFFFFFFE7U)
#define SGXVEC_USE1_VECCOMPLEXOP_SRCCHANSEL_B		(0)
#define SGXVEC_USE1_VECCOMPLEXOP_SRCCHANSEL_G		(1)
#define SGXVEC_USE1_VECCOMPLEXOP_SRCCHANSEL_R		(2)
#define SGXVEC_USE1_VECCOMPLEXOP_SRCCHANSEL_A		(3)

#define SGXVEC_USE0_VECCOMPLEXOP_DST_FIELD_LENGTH	(8)
#define SGXVEC_USE0_VECCOMPLEXOP_DST_SHIFT			(21)
#define SGXVEC_USE0_VECCOMPLEXOP_DST_CLRMSK			(0xF01FFFFFU)

#define SGXVEC_USE0_VECCOMPLEXOP_SRC1_FIELD_LENGTH	(8)
#define SGXVEC_USE0_VECCOMPLEXOP_SRC1_SHIFT			(7)
#define SGXVEC_USE0_VECCOMPLEXOP_SRC1_CLRMSK		(0xFFFFC07FU)

#define SGXVEC_USE0_VECCOMPLEXOP_WMSK_SHIFT			(0)
#define SGXVEC_USE0_VECCOMPLEXOP_WMSK_CLRMSK		(0xFFFFFFF0U)

#define SGXVEC_USE0_VECCOMPLEXOP_REGISTER_NUMBER_BITS	(7)

/*
	Vector movc instruction
*/
#define SGXVEC_USE1_VMOVC_TESTCCEXT					(0x00400000U)

#define SGXVEC_USE1_VMOVC_S0ULSEL					(0x00200000U)

#define SGXVEC_USE1_VMOVC_MTYPE_SHIFT				(14)
#define SGXVEC_USE1_VMOVC_MTYPE_CLRMSK				(0xFFFF3FFFU)
#define SGXVEC_USE1_VMOVC_MTYPE_UNCONDITIONAL		(0)
#define SGXVEC_USE1_VMOVC_MTYPE_CONDITIONAL			(1)
#define SGXVEC_USE1_VMOVC_MTYPE_U8CONDITIONAL		(2)
#define SGXVEC_USE1_VMOVC_MTYPE_RESERVED			(3)

#define SGXVEC_USE1_VMOVC_RCNT_SHIFT				(12)
#define SGXVEC_USE1_VMOVC_RCNT_CLRMSK				(0xFFFFCFFFU)
#define SGXVEC_USE1_VMOVC_RCNT_MAXIMUM				(4)

#define SGXVEC_USE1_VMOVC_NOSCHED					(0x00000800U)

#define SGXVEC_USE1_VMOVC_MDTYPE_SHIFT				(8)
#define SGXVEC_USE1_VMOVC_MDTYPE_CLRMSK				(0xFFFFF8FFU)
#define SGXVEC_USE1_VMOVC_MDTYPE_INT8				(0)
#define SGXVEC_USE1_VMOVC_MDTYPE_INT16				(1)
#define SGXVEC_USE1_VMOVC_MDTYPE_INT32				(2)
#define SGXVEC_USE1_VMOVC_MDTYPE_C10				(3)
#define SGXVEC_USE1_VMOVC_MDTYPE_F16				(4)
#define SGXVEC_USE1_VMOVC_MDTYPE_F32				(5)
#define SGXVEC_USE1_VMOVC_MDTYPE_RESERVED0			(6)
#define SGXVEC_USE1_VMOVC_MDTYPE_RESERVED1			(7)

#define SGXVEC_USE1_VMOVC_TESTCC_SHIFT				(7)
#define SGXVEC_USE1_VMOVC_TESTCC_CLRMSK				(0xFFFFFF7FU)

#define SGXVEC_USE1_VMOVC_TESTCC_STDZERO			(0)
#define SGXVEC_USE1_VMOVC_TESTCC_STDNONZERO			(1)
#define SGXVEC_USE1_VMOVC_TESTCC_EXTLTZERO			(0)
#define SGXVEC_USE1_VMOVC_TESTCC_EXTLTEZERO			(1)

#define SGXVEC_USE1_VMOVC_SWIZ_SHIFT				(3)
#define SGXVEC_USE1_VMOVC_SWIZ_CLRMSK				(0xFFFFFF87U)

#define SGXVEC_USE1_VMOVC_SWIZ_XXXX					(0)
#define SGXVEC_USE1_VMOVC_SWIZ_YYYY					(1)
#define SGXVEC_USE1_VMOVC_SWIZ_ZZZZ					(2)
#define SGXVEC_USE1_VMOVC_SWIZ_WWWW					(3)
#define SGXVEC_USE1_VMOVC_SWIZ_XYZW					(4)
#define SGXVEC_USE1_VMOVC_SWIZ_YZWW					(5)
#define SGXVEC_USE1_VMOVC_SWIZ_XYZZ					(6)
#define SGXVEC_USE1_VMOVC_SWIZ_XXYZ					(7)

#define SGXVEC_USE1_VMOVC_SWIZ_XYXY					(8)
#define SGXVEC_USE1_VMOVC_SWIZ_XYWZ					(9)
#define SGXVEC_USE1_VMOVC_SWIZ_ZXYW					(10)
#define SGXVEC_USE1_VMOVC_SWIZ_ZWZW					(11)
#define SGXVEC_USE1_VMOVC_SWIZ_YZXZ					(12)
#define SGXVEC_USE1_VMOVC_SWIZ_XXYY					(13)
#define SGXVEC_USE1_VMOVC_SWIZ_XZWW					(14)
#define SGXVEC_USE1_VMOVC_SWIZ_XYZ1					(15)

#define SGXVEC_USE0_VMOVC_WMASK_SHIFT				(24)
#define SGXVEC_USE0_VMOVC_WMASK_CLRMSK				(0xF0FFFFFFU)

#define SGXVEC_USE0_VMOVC_DST_SHIFT					(18)
#define SGXVEC_USE0_VMOVC_DST_CLRMSK				(0xFF03FFFFU)

#define SGXVEC_USE0_VMOVC_SRC0_SHIFT				(12)
#define SGXVEC_USE0_VMOVC_SRC0_CLRMSK				(0xFFFC0FFFU)

#define SGXVEC_USE0_VMOVC_SRC1_SHIFT				(6)
#define SGXVEC_USE0_VMOVC_SRC1_CLRMSK				(0xFFFFF03FU)

#define SGXVEC_USE0_VMOVC_SRC2_SHIFT				(0)
#define SGXVEC_USE0_VMOVC_SRC2_CLRMSK				(0xFFFFFFC0U)

/*
	Number of bits in the register number field when the MOV/MOVC/MOVCU8
	data type isn't C10/F16/F32.
*/
#define SGXVEC_USE0_VMOVC_NONVEC_REGISTER_NUMBER_FIELD_LENGTH \
													(6)

/*
	Number of bits in the register number field when the MOV/MOVC/MOVCU8
	data type is C10/F16/F32.
*/
#define SGXVEC_USE0_VMOVC_VEC_REGISTER_NUMBER_BITS \
													(6)

/*
	Maximum source/destination register numbers when the move data
	type (MDTYPE) is INT8, INT16 or INT32.
*/
#define SGXVEC_USE0_VMOVC_INT_REGISTER_NUMBER_MAX	(64)

/*
	Bitwise instructions.
*/
#define SGXVEC_USE1_BITWISE_RCOUNT_SHIFT			(12)
#define SGXVEC_USE1_BITWISE_RCOUNT_CLRMSK			(0xFFFF0FFFU)

/*
	Vector PCK instructions
*/
#define SGXVEC_USE1_PCK_NOSCHED						(0x00400000U)

#define SGXVEC_USE1_PCK_RCOUNT_SHIFT				(12)
#define SGXVEC_USE1_PCK_RCOUNT_CLRMSK				(0xFFFF0FFFU)

#define SGXVEC_USE0_PCK_C3SSEL_SHIFT				(19)
#define SGXVEC_USE0_PCK_C3SSEL_CLRMSK				(0xFFE7FFFFU)

#define SGXVEC_USE0_PCK_C1SSEL_SHIFT				(16)
#define SGXVEC_USE0_PCK_C1SSEL_CLRMSK				(0xFFFCFFFFU)

#define SGXVEC_USE0_PCK_C2SSEL_SHIFT				(14)
#define SGXVEC_USE0_PCK_C2SSEL_CLRMSK				(0xFFFF3FFFU)

#define SGXVEC_USE0_PCK_64BITSRC1_SHIFT				(8)
#define SGXVEC_USE0_PCK_64BITSRC1_CLRMSK			(0xFFFFC0FFU)

#define SGXVEC_USE0_PCK_F32SRC_C0SSEL_BIT1_SHIFT	(7)
#define SGXVEC_USE0_PCK_F32SRC_C0SSEL_BIT1_CLRMSK	(0xFFFFFF7FU)

#define SGXVEC_USE0_PCK_64BITSRC2_SHIFT				(1)
#define SGXVEC_USE0_PCK_64BITSRC2_CLRMSK			(0xFFFFFF81U)

#define SGXVEC_USE0_PCK_F32SRC_C0SSEL_BIT0_SHIFT	(0)
#define SGXVEC_USE0_PCK_F32SRC_C0SSEL_BIT0_CLRMSK	(0xFFFFFFFEU)

#define SGXVEC_USE0_PCK_NONF32SRC_C0SSEL_SHIFT		(0)
#define SGXVEC_USE0_PCK_NONF32SRC_C0SSEL_CLRMSK		(0xFFFFFFFCU)

/*
	The maximum number of channels which can be simultaneously converted
	between different source and destination formats.
*/
/* Between normalised U8 and F16/F32. */
#define SGXVEC_USE_PCK_U8NORM_F16F32_MAX_CONVERTS	(4)
/* Between C10 and F16/F32. */
#define SGXVEC_USE_PCK_C10_F16F32_MAX_CONVERTS		(4)
/* Between F16/F32 and F16/F32. */
#define SGXVEC_USE_PCK_F16F32_F16F32_MAX_CONVERTS	(4)
/* From other formats to F32. */
#define SGXVEC_USE_PCK_OTHER_TO_F32_MAX_CONVERTS	(1)
/* Between C10 and C10. */
#define SGXVEC_USE_PCK_C10_TO_C10_MAX_CONVERTS		(2)
/* All other format conversions. */
#define SGXVEC_USE_PCK_OTHER_MAX_CONVERTS			(2)

/*
	Number of channels which can be written for different
	destination formats when the destination register isn't
	a vector.
*/
#define SGXVEC_USE_PCK_NONVEC_32BIT_MAX_CHANS_WRITTEN		(1)
#define SGXVEC_USE_PCK_NONVEC_16BIT_MAX_CHANS_WRITTEN		(2)
#define SGXVEC_USE_PCK_NONVEC_8BIT_MAX_CHANS_WRITTEN		(4)

/*
	Maximum conversions when converting to F32 and
	the destination is a unified store register.
*/
#define SGXVEC_USE_PCK_TO_F32_UNIFIED_STORE_MAX_CONVERTS	\
													(2)

/*
	Vector test instruction
*/
/* ALUOPs for ALUSEL=F32; ALUPREC=F16 */
#define SGXVEC_USE0_TEST_ALUOP_F16_RESERVED0		(0)
#define SGXVEC_USE0_TEST_ALUOP_F16_RESERVED1		(1)
#define SGXVEC_USE0_TEST_ALUOP_F16_VADD				(2)
#define SGXVEC_USE0_TEST_ALUOP_F16_VFRC				(3)
#define SGXVEC_USE0_TEST_ALUOP_F16_FRCP				(4)
#define SGXVEC_USE0_TEST_ALUOP_F16_FRSQ				(5)
#define SGXVEC_USE0_TEST_ALUOP_F16_FLOG				(6)
#define SGXVEC_USE0_TEST_ALUOP_F16_FEXP				(7)
#define SGXVEC_USE0_TEST_ALUOP_F16_VDP				(8)
#define SGXVEC_USE0_TEST_ALUOP_F16_VMIN				(9)
#define SGXVEC_USE0_TEST_ALUOP_F16_VMAX				(10)
#define SGXVEC_USE0_TEST_ALUOP_F16_VDSX				(11)
#define SGXVEC_USE0_TEST_ALUOP_F16_VDSY				(12)
#define SGXVEC_USE0_TEST_ALUOP_F16_VMUL				(13)
#define SGXVEC_USE0_TEST_ALUOP_F16_VSUB				(14)
#define SGXVEC_USE0_TEST_ALUOP_F16_RESERVED2		(15)

/* ALUOPs for ALUSEL=F32; ALUPREC=F16 */
#define SGXVEC_USE0_TEST_ALUOP_F32_RESERVED0		(0)
#define SGXVEC_USE0_TEST_ALUOP_F32_RESERVED1		(1)
#define SGXVEC_USE0_TEST_ALUOP_F32_VADD				(2)
#define SGXVEC_USE0_TEST_ALUOP_F32_VFRC				(3)
#define SGXVEC_USE0_TEST_ALUOP_F32_FRCP				(4)
#define SGXVEC_USE0_TEST_ALUOP_F32_FRSQ				(5)
#define SGXVEC_USE0_TEST_ALUOP_F32_FLOG				(6)
#define SGXVEC_USE0_TEST_ALUOP_F32_FEXP				(7)
#define SGXVEC_USE0_TEST_ALUOP_F32_VDP				(8)
#define SGXVEC_USE0_TEST_ALUOP_F32_VMIN				(9)
#define SGXVEC_USE0_TEST_ALUOP_F32_VMAX				(10)
#define SGXVEC_USE0_TEST_ALUOP_F32_VDSX				(11)
#define SGXVEC_USE0_TEST_ALUOP_F32_VDSY				(12)
#define SGXVEC_USE0_TEST_ALUOP_F32_VMUL				(13)
#define SGXVEC_USE0_TEST_ALUOP_F32_VSUB				(14)
#define SGXVEC_USE0_TEST_ALUOP_F32_RESERVED2		(15)

/* New ALUOPs for ALUSEL=I8 */
#define SGXVEC_USE0_TEST_ALUOP_I8_SABLND			(9)

/* New ALUOPs for ALUSEL=I16 */
#define SGXVEC_USE0_TEST_ALUOP_I16_SUB32			(14)
#define SGXVEC_USE0_TEST_ALUOP_I16_SUBU32			(15)

/*
	Source 1 negate modifier.
*/
#define SGXVEC_USE1_TEST_NEGATESRC1					(0x00040000U)

/*
	New channel combine option.
*/
#define SGXVEC_USE1_TEST_CHANCC_PERCHAN				(6)

#define SGXVEC_USE1_TEST_PREC_SHIFT					(15)
#define SGXVEC_USE1_TEST_PREC_CLRMSK				(0xFFFF7FFFU)

#define SGXVEC_USE1_TEST_PREC_ALUFLOAT_F16			(0)
#define SGXVEC_USE1_TEST_PREC_ALUFLOAT_F32			(1)

#define SGXVEC_USE1_TEST_PREC_ALUI16_I16			(0)
#define SGXVEC_USE1_TEST_PREC_ALUI16_I32			(1)

#define SGXVEC_USE1_TEST_PREC_ALUI8_I8				(0)
#define SGXVEC_USE1_TEST_PREC_ALUI8_I10				(1)

#define SGXVEC_USE1_TEST_PREC_ALUBITWISE_BITWISE	(0)
#define SGXVEC_USE1_TEST_PREC_ALUBITWISE_RESERVED	(1)

#define SGXVEC_USE1_TEST_VSCOMP						(0x00004000U)

#define SGXVEC_USE1_TEST_RCNT_SHIFT					(12)
#define SGXVEC_USE1_TEST_RCNT_CLRMSK				(0xFFFFCFFFU)
#define SGXVEC_USE1_TEST_RCNT_MAXIMUM				(4)

#define SGXVEC_USE1_TESTMASK_TSTTYPE_8BITMASK		(0)
#define SGXVEC_USE1_TESTMASK_TSTTYPE_PRECMASK		(1)
#define SGXVEC_USE1_TESTMASK_TSTTYPE_NUMMASK		(2)
#define SGXVEC_USE1_TESTMASK_TSTTYPE_RESERVED		(3)

/*
	The number field is effectively 8 bits long (considering the register number in 32-bit units)
	but the LSB is always zero.
*/
#define _SGXVEC_USE_TEST_VEC_REGISTER_NUMBER_BITS	(7)
#define SGXVEC_USE_TEST_VEC_REGISTER_FIELD_LENGTH	(_SGXVEC_USE_TEST_VEC_REGISTER_NUMBER_BITS + 1)

/*
	IMA32 instruction changes.
*/
#define SGXVEC_USE1_IMA32_STEP_SHIFT				(20)
#define SGXVEC_USE1_IMA32_STEP_CLRMSK				(0xFFCFFFFFU)
#define SGXVEC_USE1_IMA32_STEP_STEP1				(0)
#define SGXVEC_USE1_IMA32_STEP_STEP2				(1)
#define SGXVEC_USE1_IMA32_STEP_RESERVED0			(2)
#define SGXVEC_USE1_IMA32_STEP_RESERVED1			(3)

/*
	SMP instruction changes.
*/
#define SGXVEC_USE1_SMP_MINPACK						(0x00080000U)

#define SGXVEC_USE1_SMP_FCONV_SHIFT					(14)
#define SGXVEC_USE1_SMP_FCONV_CLRMSK				(0xFFFF3FFFU)
#define SGXVEC_USE1_SMP_FCONV_NONE					(0)
#define SGXVEC_USE1_SMP_FCONV_RESERVED				(1)
#define SGXVEC_USE1_SMP_FCONV_F16					(2)
#define SGXVEC_USE1_SMP_FCONV_F32					(3)

#define SGXVEC_USE1_SMP_SBMODE_SHIFT				(5)
#define SGXVEC_USE1_SMP_SBMODE_CLRMSK				(0xFFFFFF9FU)
#define SGXVEC_USE1_SMP_SBMODE_NONE					(0)
#define SGXVEC_USE1_SMP_SBMODE_RAWDATA				(1)
#define SGXVEC_USE1_SMP_SBMODE_COEFFS				(2)
#define SGXVEC_USE1_SMP_SBMODE_BOTH					(3)

#define SGXVEC_USE_SMP_SRC_FIELD_LENGTH				(8)

/*
	Size (in dwords) of the space required for the packed bilinear fractions
	returned by the SMP instruction when using SBMODE=BOTH.
*/
#define SGXVEC_USE_SMP_IRSD_BILINEAR_FRACTIONS_SIZE (2)

/*
	Number of unfiltered texture samples for each mipmap level
	returned by the SMP instruction when using SBMODE=BOTH.
*/
#define SGXVEC_USE_SMP_IRSD_BILINEAR_SAMPLE_COUNT	(4)

/*
	Number of registers written by a texture sample using SRD=COEFFS
*/
#define SGXVEC_USE_SMP_SRD_COEFFS_RESULT_LENGTH				(1)

/*
	Format of the data returned by a texture sample using SRD=COEFFS

	Bit		Register offset	Description
	31..24	0				LOD value
	23..16	0				Trilinear fraction
	15..8	0				Bilinear V fraction
	7..0	0				Bilinear U fraction
*/
#define SGXVEC_USE_SMP_SRD_COEFFS0_UFRACTION_SHIFT			(0)
#define SGXVEC_USE_SMP_SRD_COEFFS0_UFRACTION_CLRMSK			(0xFFFFFF00)

#define SGXVEC_USE_SMP_SRD_COEFFS0_VFRACTION_SHIFT			(8)
#define SGXVEC_USE_SMP_SRD_COEFFS0_VFRACTION_CLRMSK			(0xFFFF00FF)

#define SGXVEC_USE_SMP_SRD_COEFFS0_TRILINEARFRACTION_SHIFT	(16)
#define SGXVEC_USE_SMP_SRD_COEFFS0_TRILINEARFRACTION_CLRMSK	(0xFF00FFFF)

#define SGXVEC_USE_SMP_SRD_COEFFS0_LOD_SHIFT				(24)
#define SGXVEC_USE_SMP_SRD_COEFFS0_LOD_CLRMSK				(0x00FFFFFF)

/*
	The range of 32-bit registers read when sampling a 3D texture using
	supplied gradients in F32 format. The layout is:-

	Offset:		0		1		2		3		4		5		6
	Contents:	dUdX	dVdX	dSdX	__		dUdY	dVdY	dSdY
*/
#define SGXVEC_USE_SMP_F32_3D_GRADIENTS_SIZE				(7)

/*
	The range of 32-bit registers read when sampling a 3D texture using
	supplied gradients in F16 format. The layout is:-

	Offset:		0				1				2				3
	Contents:	(dUdX, dVdX)	(dSdX, __)		(dUdY, dVdY)	(dSdY, __)
*/
#define SGXVEC_USE_SMP_F16_3D_GRADIENTS_SIZE				(4)

/*
	LD/ST instruction changes.
*/
#define SGXVEC_USE1_LDST_DTYPE_QWORD				(3)

#if defined(SUPPORT_SGX_FEATURE_USE_LD_ST_ATOMIC_OPS) || defined(SGX_FEATURE_USE_LD_ST_ATOMIC_OPS)
/*
	LD instructions with atomic operations.
*/
#define SGXVEC_USE1_LD_AMODE_ATOMIC					(3)

#define SGXVEC_USE1_LD_ATOMIC_OP_SHIFT				(12)
#define SGXVEC_USE1_LD_ATOMIC_OP_CLRMSK				(0xFFFF0FFF)

#define SGXVEC_USE1_LD_ATOMIC_OP_ADD				(0)
#define SGXVEC_USE1_LD_ATOMIC_OP_SUB				(1)
#define SGXVEC_USE1_LD_ATOMIC_OP_XCHG				(2)
#define SGXVEC_USE1_LD_ATOMIC_OP_RESERVED0			(3)
#define SGXVEC_USE1_LD_ATOMIC_OP_MIN				(4)
#define SGXVEC_USE1_LD_ATOMIC_OP_MAX				(5)
#define SGXVEC_USE1_LD_ATOMIC_OP_AND				(6)
#define SGXVEC_USE1_LD_ATOMIC_OP_OR					(7)
#define SGXVEC_USE1_LD_ATOMIC_OP_XOR				(8)

/* Replaces EURASIA_USE1_LDST_DTYPE */
#define SGXVEC_USE1_LD_ATOMIC_DATASGN				(0x000000010)

#endif /* defined(SUPPORT_SGX_FEATURE_USE_LD_ST_ATOMIC_OPS) || defined(SGX_FEATURE_USE_LD_ST_ATOMIC_OPS) */

/*
	Branch instruction changes
*/
#define SGXVEC_USE1_FLOWCTRL_PWAIT					(0x00002000U)

#if defined(SUPPORT_SGX_FEATURE_USE_BRANCH_ALL_ANY_INSTANCES) || defined(SGX_FEATURE_USE_BRANCH_ALL_ANY_INSTANCES)
#define SGXVEC_USE0_FLOWCTRL_ALLINSTANCES			(0x00100000U)

#define SGXVEC_USE0_FLOWCTRL_ANYINSTANCES			(0x00200000U)
#endif /* defined(SUPPORT_SGX_FEATURE_USE_BRANCH_ALL_ANY_INSTANCES) || defined(SGX_FEATURE_USE_BRANCH_ALL_ANY_INSTANCES) */

#if defined(SUPPORT_SGX_FEATURE_USE_INTEGER_CONDITIONALS) || defined(SGX_FEATURE_USE_INTEGER_CONDITIONALS)
/*
	Integer conditional instructions
*/
#define EURASIA_USE1_SPECIAL_OPCAT_CND				(1)

#define SGXVEC_USE1_CND_NOSCHED						(0x00000800)

#define SGXVEC_USE1_CND_OP2_SHIFT					(6)
#define SGXVEC_USE1_CND_OP2_CLRMSK					(0xFFFFFE3F)
#define SGXVEC_USE1_CND_OP2_CNDST					(0)
#define SGXVEC_USE1_CND_OP2_CNDEF					(1)
#define SGXVEC_USE1_CND_OP2_CNDSM					(2)
#define SGXVEC_USE1_CND_OP2_CNDLT					(3)
#define SGXVEC_USE1_CND_OP2_CNDEND					(4)

#define SGXVEC_USE1_CND_PCND_SHIFT					(2)
#define SGXVEC_USE1_CND_PCND_CLRMSK					(0xFFFFFFC3)
#define SGXVEC_USE1_CND_PCND_P0						(0)
#define SGXVEC_USE1_CND_PCND_P1						(1)
#define SGXVEC_USE1_CND_PCND_P2						(2)
#define SGXVEC_USE1_CND_PCND_P3						(3)
#define SGXVEC_USE1_CND_PCND_NOTP0					(4)
#define SGXVEC_USE1_CND_PCND_NOTP1					(5)
#define SGXVEC_USE1_CND_PCND_NOTP2					(6)
#define SGXVEC_USE1_CND_PCND_NOTP3					(7)
#define SGXVEC_USE1_CND_PCND_TRUE					(8)
#define SGXVEC_USE1_CND_PCND_RESERVED0				(9)
#define SGXVEC_USE1_CND_PCND_RESERVED1				(10)
#define SGXVEC_USE1_CND_PCND_RESERVED2				(11)
#define SGXVEC_USE1_CND_PCND_RESERVED3				(12)
#define SGXVEC_USE1_CND_PCND_RESERVED4				(13)
#define SGXVEC_USE1_CND_PCND_RESERVED5				(14)
#define SGXVEC_USE1_CND_PCND_FALSE					(15)

#define SGXVEC_USE0_CNDLT_PDSTLOOP_SHIFT			(19)
#define SGXVEC_USE0_CNDLT_PDSTLOOP_CLRMSK			(0xFFE7FFFF)

#define SGXVEC_USE0_CND_ADJUST_SHIFT				(0)
#define SGXVEC_USE0_CND_ADJUST_CLRMSK				(0xFFFFFFFC)
#define SGXVEC_USE0_CND_ADJUST_MAXIMUM				(2)

#define SGXVEC_USE_CND_MAXIMUM_PREDICATE			(3)

#endif /* defined(SUPPORT_SGX_FEATURE_USE_INTEGER_CONDITIONALS) || defined(SGX_FEATURE_USE_INTEGER_CONDITIONALS) */

/*
	LDR/STR
*/
#define SGXVEC_USE1_LDRSTR_RCNT_SHIFT				(12)
#define SGXVEC_USE1_LDRSTR_RCNT_CLRMSK				(0xFFFF0FFFU)
#define SGXVEC_USE1_LDRSTR_RCNT_MAXIMUM				(16)

#define SGXVEC_USE1_LDRSTR_SRC2EXT2_SHIFT			(2)
#define SGXVEC_USE1_LDRSTR_SRC2EXT2_CLRMSK			(0xFFFFFFC3U)
#define SGXVEC_USE1_LDRSTR_SRC2EXT2_INTERNALSHIFT	(14)

#define SGXVEC_USE1_LDRSTR_STR_SPRED_SHIFT			(9)
#define SGXVEC_USE1_LDRSTR_STR_SPRED_CLRMSK			(0xFFFFF9FFU)

#define SGXVEC_USE_LDRSTR_GLOBREG_MAX_NUM			((1UL << 18) - 1)

/*
	Sub-component indexing instructions
*/
#define SGXVEC_USE1_OTHER2_OP2_IDXSCR				(3)
#define SGXVEC_USE1_OTHER2_OP2_IDXSCW				(4)

#define SGXVEC_USE1_OTHER2_IDXSC_NOSCHED			(0x00000800U)

#define SGXVEC_USE1_OTHER2_IDXSC_COMPCOUNT_SHIFT	(10)
#define SGXVEC_USE1_OTHER2_IDXSC_COMPCOUNT_CLRMSK	(0xFFFFFBFFU)

#define SGXVEC_USE1_OTHER2_IDXSC_COMPCOUNT_1		(0)
#define SGXVEC_USE1_OTHER2_IDXSC_COMPCOUNT_2		(1)

#define SGXVEC_USE1_OTHER2_IDXSC_FORMAT_SHIFT		(8)
#define SGXVEC_USE1_OTHER2_IDXSC_FORMAT_CLRMSK		(0xFFFFFCFFU)

#define SGXVEC_USE1_OTHER2_IDXSC_FORMAT_8888		(0)
#define SGXVEC_USE1_OTHER2_IDXSC_FORMAT_10101010	(1)
#define SGXVEC_USE1_OTHER2_IDXSC_FORMAT_16161616	(2)
#define SGXVEC_USE1_OTHER2_IDXSC_FORMAT_3232		(3)

#define SGXVEC_USE1_OTHER2_IDXSC_INDEXREG_SHIFT		(3)
#define SGXVEC_USE1_OTHER2_IDXSC_INDEXREG_CLRMSK	(0xFFFFFFF7U)

#define SGXVEC_USE1_OTHER2_IDXSC_INDEXREG_LOW		(0)
#define SGXVEC_USE1_OTHER2_IDXSC_INDEXREG_HIGH		(1)

#define SGXVEC_USE0_OTHER2_IDXSC_INDEXOFF_SHIFT		(0)
#define SGXVEC_USE0_OTHER2_IDXSC_INDEXOFF_CLRMSK	(0xFFFFFF80U)
#define SGXVEC_USE0_OTHER2_IDXSC_INDEXOFF_MAXIMUM	(127)

/*
	Emit instruction definitions.
*/
#define SGXVEC_USE_EMIT_SRC_FIELD_LENGTH			(8)

/*
	Short vector predicates. Used by dual-issue and
	VMAD instructions.
*/
#define SGXVEC_USE_VEC_SVPRED_NONE					(0)
#define SGXVEC_USE_VEC_SVPRED_P0					(1)
#define SGXVEC_USE_VEC_SVPRED_NOTP0					(2)
#define SGXVEC_USE_VEC_SVPRED_PERCHAN				(3)

/* Range of predicate registers available without the negate flag. */
#define SGXVEC_USE_SVPRED_NUM_PREDICATES			(1)
/* Range of predicate registers available with the negate flag. */
#define SGXVEC_USE_SVPRED_NUM_NEGATED_PREDICATES	(1)

/*
	Extended vector predicates. Used by single-issue
	and two source vector instructions.
*/
#define SGXVEC_USE_VEC_EVPRED_NONE					(0)
#define SGXVEC_USE_VEC_EVPRED_P0					(1)
#define SGXVEC_USE_VEC_EVPRED_P1					(2)
#define SGXVEC_USE_VEC_EVPRED_P2					(3)
#define SGXVEC_USE_VEC_EVPRED_NOTP0					(4)
#define SGXVEC_USE_VEC_EVPRED_NOTP1					(5)
#define SGXVEC_USE_VEC_EVPRED_NOTP2					(6)
#define SGXVEC_USE_VEC_EVPRED_PERCHAN				(7)

/* Range of predicate registers available without the negate flag. */
#define SGXVEC_USE_EVPRED_NUM_PREDICATES			(3)
/* Range of predicate registers available with the negate flag. */
#define SGXVEC_USE_EVPRED_NUM_NEGATED_PREDICATES	(3)

/*
	Vector instruction swizzles.
*/

/*
	Vec3 swizzles.
*/

#define SGXVEC_USE_VEC3_SWIZ_STD_XXX			(0)
#define SGXVEC_USE_VEC3_SWIZ_STD_YYY			(1)
#define SGXVEC_USE_VEC3_SWIZ_STD_ZZZ			(2)
#define SGXVEC_USE_VEC3_SWIZ_STD_WWW			(3)
#define SGXVEC_USE_VEC3_SWIZ_STD_XYZ			(4)
#define SGXVEC_USE_VEC3_SWIZ_STD_YZW			(5)
#define SGXVEC_USE_VEC3_SWIZ_STD_XXY			(6)
#define SGXVEC_USE_VEC3_SWIZ_STD_XYX			(7)
#define SGXVEC_USE_VEC3_SWIZ_STD_YYX			(8)
#define SGXVEC_USE_VEC3_SWIZ_STD_YYZ			(9)
#define SGXVEC_USE_VEC3_SWIZ_STD_ZXY			(10)
#define SGXVEC_USE_VEC3_SWIZ_STD_XZY			(11)
#define SGXVEC_USE_VEC3_SWIZ_STD_YZX			(12)
#define SGXVEC_USE_VEC3_SWIZ_STD_ZYX			(13)
#define SGXVEC_USE_VEC3_SWIZ_STD_ZZY			(14)
#define SGXVEC_USE_VEC3_SWIZ_STD_XY1			(15)

#define SGXVEC_USE_VEC3_SWIZ_EXT_XYY			(0)
#define SGXVEC_USE_VEC3_SWIZ_EXT_YXY			(1)
#define SGXVEC_USE_VEC3_SWIZ_EXT_XXZ			(2)
#define SGXVEC_USE_VEC3_SWIZ_EXT_YXX			(3)
#define SGXVEC_USE_VEC3_SWIZ_EXT_XY0			(4)
#define SGXVEC_USE_VEC3_SWIZ_EXT_X10			(5)
#define SGXVEC_USE_VEC3_SWIZ_EXT_000			(6)
#define SGXVEC_USE_VEC3_SWIZ_EXT_111			(7)
#define SGXVEC_USE_VEC3_SWIZ_EXT_HALF			(8)
#define SGXVEC_USE_VEC3_SWIZ_EXT_222			(9)
#define SGXVEC_USE_VEC3_SWIZ_EXT_X00			(10)

/*
	Vec4 swizzles.
*/

#define SGXVEC_USE_VEC4_SWIZ_STD_XXXX			(0)
#define SGXVEC_USE_VEC4_SWIZ_STD_YYYY			(1)
#define SGXVEC_USE_VEC4_SWIZ_STD_ZZZZ			(2)
#define SGXVEC_USE_VEC4_SWIZ_STD_WWWW			(3)
#define SGXVEC_USE_VEC4_SWIZ_STD_XYZW			(4)
#define SGXVEC_USE_VEC4_SWIZ_STD_YZWW			(5)
#define SGXVEC_USE_VEC4_SWIZ_STD_XYZZ			(6)
#define SGXVEC_USE_VEC4_SWIZ_STD_XXYZ			(7)
#define SGXVEC_USE_VEC4_SWIZ_STD_XYXY			(8)
#define SGXVEC_USE_VEC4_SWIZ_STD_XYWZ			(9)
#define SGXVEC_USE_VEC4_SWIZ_STD_ZXYW			(10)
#define SGXVEC_USE_VEC4_SWIZ_STD_ZWZW			(11)
#define SGXVEC_USE_VEC4_SWIZ_STD_YZXZ			(12)
#define SGXVEC_USE_VEC4_SWIZ_STD_XXYY			(13)
#define SGXVEC_USE_VEC4_SWIZ_STD_XZWW			(14)
#define SGXVEC_USE_VEC4_SWIZ_STD_XYZ1			(15)


#define SGXVEC_USE_VEC4_SWIZ_EXT_YZXW			(0)
#define SGXVEC_USE_VEC4_SWIZ_EXT_ZWXY			(1)
#define SGXVEC_USE_VEC4_SWIZ_EXT_XZWY			(2)
#define SGXVEC_USE_VEC4_SWIZ_EXT_YYWW			(3)
#define SGXVEC_USE_VEC4_SWIZ_EXT_WYZW			(4)
#define SGXVEC_USE_VEC4_SWIZ_EXT_WZWZ			(5)
#define SGXVEC_USE_VEC4_SWIZ_EXT_XYZX			(6)
#define SGXVEC_USE_VEC4_SWIZ_EXT_ZZWW			(7)
#define SGXVEC_USE_VEC4_SWIZ_EXT_XWZX			(8)
#define SGXVEC_USE_VEC4_SWIZ_EXT_YYYX			(9)
#define SGXVEC_USE_VEC4_SWIZ_EXT_YYYZ			(10)
#define SGXVEC_USE_VEC4_SWIZ_EXT_XZYW			(11)
#define SGXVEC_USE_VEC4_SWIZ_EXT_XXXY			(12)
#define SGXVEC_USE_VEC4_SWIZ_EXT_ZYXW			(13)
#define SGXVEC_USE_VEC4_SWIZ_EXT_YYZZ			(14)
#define SGXVEC_USE_VEC4_SWIZ_EXT_ZZZY			(15)

/*
	Hardware constants.
*/
#define SGXVEC_USE_SPECIAL_CONSTANT_ZERO_ZERO										(0)
#define SGXVEC_USE_SPECIAL_CONSTANT_ZERO_ONE										(1)
#define SGXVEC_USE_SPECIAL_CONSTANT_ONE_ZERO										(2)
#define SGXVEC_USE_SPECIAL_CONSTANT_ONE_ONE											(3)
#define SGXVEC_USE_SPECIAL_CONSTANT_TWO_FOUR										(4)
#define SGXVEC_USE_SPECIAL_CONSTANT_8_16											(5)
#define SGXVEC_USE_SPECIAL_CONSTANT_32_64											(6)
#define SGXVEC_USE_SPECIAL_CONSTANT_128_256											(7)
#define SGXVEC_USE_SPECIAL_CONSTANT_512_1024										(8)
#define SGXVEC_USE_SPECIAL_CONSTANT_2048_4096										(9)
#define SGXVEC_USE_SPECIAL_CONSTANT_8192_16384										(10)
#define SGXVEC_USE_SPECIAL_CONSTANT_32768_65536										(11)
#define SGXVEC_USE_SPECIAL_CONSTANT_1OVER2_1OVER4									(12)
#define SGXVEC_USE_SPECIAL_CONSTANT_1OVER8_1OVER16									(13)
#define SGXVEC_USE_SPECIAL_CONSTANT_1OVER32_1OVER64									(14)
#define SGXVEC_USE_SPECIAL_CONSTANT_1OVER128_1OVER256								(15)
#define SGXVEC_USE_SPECIAL_CONSTANT_1OVER512_1OVER1024								(16)
#define SGXVEC_USE_SPECIAL_CONSTANT_1OVER2048_1OVER4096								(17)
#define SGXVEC_USE_SPECIAL_CONSTANT_1OVER8192_1OVER16384							(18)
#define SGXVEC_USE_SPECIAL_CONSTANT_1OVER32768_1OVER65536							(19)
#define SGXVEC_USE_SPECIAL_CONSTANT_E_1OVERE										(20)
#define SGXVEC_USE_SPECIAL_CONSTANT_SQRT2_1OVERSQRT2								(21)
#define SGXVEC_USE_SPECIAL_CONSTANT_PI_PIOVER2										(22)
#define SGXVEC_USE_SPECIAL_CONSTANT_PIOVER4_PIOVER8									(23)
#define SGXVEC_USE_SPECIAL_CONSTANT_2PI_4PI											(24)
#define SGXVEC_USE_SPECIAL_CONSTANT_8PI_ZERO										(25)
#define SGXVEC_USE_SPECIAL_CONSTANT_1OVER65536_1OVER32768							(26)
#define SGXVEC_USE_SPECIAL_CONSTANT_1OVER65535_1OVER32767							(27)
#define SGXVEC_USE_SPECIAL_CONSTANT_TAYLORSERIES1									(28)
#define SGXVEC_USE_SPECIAL_CONSTANT_TAYLORSERIES2									(29)
#define SGXVEC_USE_SPECIAL_CONSTANT_TAYLORSERIES3									(30)
#define SGXVEC_USE_SPECIAL_CONSTANT_TAYLORSERIES4									(31)
#define SGXVEC_USE_SPECIAL_CONSTANT_F16_ZERO_ZERO_ZERO_ONE							(32)
#define SGXVEC_USE_SPECIAL_CONSTANT_F16_ZERO_ZERO_ZERO_ZERO							(33)
#define SGXVEC_USE_SPECIAL_CONSTANT_F16_ONE_ONE_ONE_ONE								(34)
#define SGXVEC_USE_SPECIAL_CONSTANT_F16_2_4_8_16									(35)
#define SGXVEC_USE_SPECIAL_CONSTANT_F16_32_64_128_256								(36)
#define SGXVEC_USE_SPECIAL_CONSTANT_F16_512_1024_2048_4096							(37)
#define SGXVEC_USE_SPECIAL_CONSTANT_F16_8192_16384_32768_ZERO						(38)
#define SGXVEC_USE_SPECIAL_CONSTANT_F16_1OVER2_1OVER4_1OVER8_1OVER16				(39)
#define SGXVEC_USE_SPECIAL_CONSTANT_F16_1OVER32_1OVER64_1OVER128_1OVER256			(40)
#define SGXVEC_USE_SPECIAL_CONSTANT_F16_1OVER512_1OVER1024_1OVER2048_1OVER4096		(41)
#define SGXVEC_USE_SPECIAL_CONSTANT_F16_1OVER8192_1OVER16384_ZERO_ZERO				(42)
#define SGXVEC_USE_SPECIAL_CONSTANT_F16_E_1OVERE_ZERO_ZERO							(43)
#define SGXVEC_USE_SPECIAL_CONSTANT_F16_SQRT2_1OVERSQRT2_ZERO_ZERO					(44)
#define SGXVEC_USE_SPECIAL_CONSTANT_F16_PI_PIOVER2_PIOVER4_PIOVER8					(45)
#define SGXVEC_USE_SPECIAL_CONSTANT_F16_2PI_4PI_8PI_ZERO							(46)
#define SGXVEC_USE_SPECIAL_CONSTANT_F16_ZERO_ZERO_ZERO_ZERO_VER1					(47)
#define SGXVEC_USE_SPECIAL_CONSTANT_F16_TAYLORSERIES12								(48)
#define SGXVEC_USE_SPECIAL_CONSTANT_F16_TAYLORSERIES34								(49)
#define SGXVEC_USE_SPECIAL_CONSTANT_RESERVED0										(50)
#define SGXVEC_USE_SPECIAL_CONSTANT_RESERVED1										(51)
#define SGXVEC_USE_SPECIAL_CONSTANT_RESERVED2										(52)
#define SGXVEC_USE_SPECIAL_CONSTANT_RESERVED3										(53)
#define SGXVEC_USE_SPECIAL_CONSTANT_RESERVED4										(54)
#define SGXVEC_USE_SPECIAL_CONSTANT_RESERVED5										(55)
#define SGXVEC_USE_SPECIAL_CONSTANT_FFFFFFFF										(56)
#define SGXVEC_USE_SPECIAL_CONSTANT_FFFFFFFF_VER1									(57)
#define SGXVEC_USE_SPECIAL_CONSTANT_FFFFFFFF_VER2									(58)
#define SGXVEC_USE_SPECIAL_CONSTANT_FFFFFFFF_VER3									(59)
#define SGXVEC_USE_SPECIAL_CONSTANT_7FFF7FFF										(60)
#define SGXVEC_USE_SPECIAL_CONSTANT_7FFF7FFF_VER1									(61)
#define SGXVEC_USE_SPECIAL_CONSTANT_7FFF7FFF_VER2									(62)
#define SGXVEC_USE_SPECIAL_CONSTANT_7FFF7FFF_VER3									(63)

#define SGXVEC_USE_SPECIAL_NUM_FLOAT_CONSTANTS										(64)

#define SGXVEC_USE_SPECIAL_CONSTANT_WIDTH											(2)

#endif	/* _SGXVEC34USEDEFS_H_ */

/* EOF */
